C8051F850-B-GM Datasheet, PDF (77/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
14.2. ADC Operation
The ADC is clocked by an adjustable conversion clock (SARCLK). SARCLK is a divided version of the selected
system clock when burst mode is disabled (ADBMEN = 0), or a divided version of the high-frequency oscillator
when burst mode is enabled (ADBMEN = 1). The clock divide value is determined by the ADSC bits in the ADC0CF
register. In most applications, SARCLK should be adjusted to operate as fast as possible, without exceeding the
maximum electrical specifications. The SARCLK does not directly determine sampling times or sampling rates.
14.2.1. Starting a Conversion
A conversion can be initiated in many ways, depending on the programmed states of the ADC0 Start of Conversion
Mode field (ADCM) in register ADC0CN0. Conversions may be initiated by one of the following:
1. Writing a 1 to the ADBUSY bit of register ADC0CN0 (software-triggered)
2. A timer overflow (see the ADC0CN0 register and the timer section for timer options)
3. A rising edge on the CNVSTR input signal (external pin-triggered)
Writing a 1 to ADBUSY provides software control of ADC0 whereby conversions are performed "on-demand". All
other trigger sources occur autonomous to code execution. When the conversion is complete, the ADC posts the
result to its output register and sets the ADC interrupt flag (ADINT). ADINT may be used to trigger a system
interrupts, if enabled, or polled by firmware.
During conversion, the ADBUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. However,
when polling for ADC conversion completions, the ADC0 interrupt flag (ADINT) should be used instead of the
ADBUSY bit. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when the conversion is
complete.
Important Note About Using CNVSTR: When the CNVSTR input is used as the ADC0 conversion source, the
associated port pin should be skipped in the crossbar settings.
14.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be
accurate. The minimum tracking time is given in the electrical specifications tables. The ADTM bit in register
ADC0CN0 controls the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0
input is continuously tracked, except when a conversion is in progress. A conversion will begin immediately when
the start-of-conversion trigger occurs.
When the ADTM bit is logic 1, each conversion is preceded by a tracking period of 4 SAR clocks (after the start-of-
conversion signal) for any internal (non-CNVSTR) conversion trigger source. When the CNVSTR signal is used to
initiate conversions with ADTM set to 1, ADC0 tracks only when CNVSTR is low; conversion begins on the rising
edge of CNVSTR (see Figure 14.2). Setting ADTM to 1 is primarily useful when AMUX settings are frequently
changed and conversions are started using the ADBUSY bit.
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