C8051F850-B-GM Datasheet, PDF (180/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
21.7. Port I/O and Pin Configuration Control Registers
Register 21.1. XBR0: Port I/O Crossbar 0
Bit
7
Name SYSCKE
Type
RW
Reset
0
SFR Address: 0xE1
Bit
Name
7
SYSCKE
6
CP1AE
5
CP1E
4
CP0AE
3
CP0E
2
SMB0E
1
SPI0E
0
URT0E
6
CP1AE
RW
0
5
CP1E
RW
0
4
CP0AE
RW
0
3
CP0E
RW
0
2
SMB0E
RW
0
1
SPI0E
RW
0
0
URT0E
RW
0
Table 21.4. XBR0 Register Bit Descriptions
Function
SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SMBus0 I/O Enable.
0: SMBus0 I/O unavailable at Port pins.
1: SMBus0 I/O routed to Port pins.
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4 GPIO pins.
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX, RX routed to Port pins P0.4 and P0.5.
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Preliminary Rev 0.6