C8051F850-B-GM Datasheet, PDF (205/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Register 22.4. SPI0DAT: SPI0 Data
Bit
7
6
5
4
3
2
1
0
Name
SPI0DAT
Type
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xA3
Table 22.4. SPI0DAT Register Bit Descriptions
Bit
Name
Function
7:0
SPI0DAT SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0-
DAT places the data into the transmit buffer and initiates a transfer when in master mode.
A read of SPI0DAT returns the contents of the receive buffer.
Register 22.5. RSTSRC: Reset Source
Bit
Name
7
Reserved
6
FERROR
5
C0RSEF
4
SWRSF
3
2
WDTRSF MCDRSF
1
PORSF
0
PINRSF
Type
R
R
RW
RW
R
RW
RW
R
Reset
0
X
X
X
X
X
X
X
SFR Address: 0xEF
Table 22.5. RSTSRC Register Bit Descriptions
Bit
Name
Function
7
Reserved Must write reset value.
6
FERROR Flash Error Reset Flag.
This read-only bit is set to 1 if a flash read/write/erase error caused the last reset.
5
C0RSEF Comparator0 Reset Enable and Flag.
Read: This bit reads 1 if Comparator0 caused the last reset.
Write: Writing a 1 to this bit enables Comparator0 (active-low) as a reset source.
Notes:
1. Reads and writes of the RSTSRC register access different logic in the device. Reading the register always returns
status information to indicate the source of the most recent reset. Writing to the register activates certain options as
reset sources. It is recommended to not use any kind of read-modify-write operation on this register.
2. When the PORSF bit reads back 1 all other RSTSRC flags are indeterminate.
3. Writing 1 to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset.
Preliminary Rev 0.6
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