C8051F850-B-GM Datasheet, PDF (13/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Table 1.7. ADC (Continued)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Offset Error
E_OFF
12 Bit Mode, VREF = 1.65 V
–2
0
10 Bit Mode, VREF = 1.65 V
–1
0
2
LSB
1
LSB
Offset Temperature Coeffi-
cient
TC_OFF
— 0.004 — LSB/°C
Slope Error
E_M
12 Bit Mode
–0.07 –0.02 0.02
%
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput, using AGND pin
Signal-to-Noise
SNR
12 Bit Mode
TBD 66
—
dB
10 Bit Mode
TBD 60
—
dB
Signal-to-Noise Plus Distor- SNDR
tion
12 Bit Mode
10 Bit Mode
TBD 66
—
dB
TBD 60
—
dB
Total Harmonic Distortion
(Up to 5th Harmonic)
THD
12 Bit Mode
10 Bit Mode
—
71
—
dB
—
70
—
dB
Spurious-Free Dynamic
Range
SFDR
12 Bit Mode
10 Bit Mode
—
–79
—
dB
—
–74
—
dB
*Note: Absolute input pin voltage is limited by the V_DD supply.
Preliminary Rev 0.6
13