C8051F850-B-GM Datasheet, PDF (124/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Register 17.2. CPT0MD: Comparator 0 Mode
Bit
7
6
5
4
3
2
1
0
Name CPLOUT Reserved CPRIE
CPFIE
Reserved
CPMD
Type
RW
R
RW
RW
R
RW
Reset
0
0
0
0
0
0
1
0
SFR Address: 0x9D
Table 17.6. CPT0MD Register Bit Descriptions
Bit
Name
Function
7
CPLOUT Comparator 0 Latched Output Flag.
This bit represents the comparator output value at the most recent PCA counter overflow.
0: Comparator output was logic low at last PCA overflow.
1: Comparator output was logic high at last PCA overflow.
6
Reserved Must write reset value.
5
CPRIE Comparator 0 Rising-Edge Interrupt Enable.
0: Comparator Rising-edge interrupt disabled.
1: Comparator Rising-edge interrupt enabled.
4
CPFIE Comparator 0 Falling-Edge Interrupt Enable.
0: Comparator Falling-edge interrupt disabled.
1: Comparator Falling-edge interrupt enabled.
3:2
Reserved Must write reset value.
1:0
CPMD Comparator 0 Mode Select.
These bits affect the response time and power consumption of the comparator.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
128
Preliminary Rev 0.6