C8051F850-B-GM Datasheet, PDF (244/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Register 24.6. SMB0DAT: SMBus0 Data
Bit
7
6
5
4
3
2
1
0
Name
SMB0DAT
Type
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xC2
Table 24.12. SMB0DAT Register Bit Descriptions
Bit
Name
Function
7:0 SMB0DAT SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial
interface or a byte that has just been received on the SMBus0 serial interface. The CPU
can safely read from or write to this register whenever the SI serial interrupt flag is set to
logic 1. The serial data in the register remains stable as long as the SI flag is set. When
the SI flag is not set, the system may be in the process of shifting data in/out and the
CPU should not attempt to access this register.
Preliminary Rev 0.6
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