C8051F850-B-GM Datasheet, PDF (196/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Register 21.17. P2: Port 2 Pin Latch
Bit
7
6
5
4
3
2
1
0
Name
Reserved
P2
Type
R
RW
Reset
0
0
0
0
0
0
1
1
SFR Address: 0xA0 (bit-addressable)
Table 21.20. P2 Register Bit Descriptions
Bit
Name
7:2
Reserved Must write reset value.
Function
1:0
P2
Port 2 Data.
Writing this register sets the port latch logic value for the associated I/O pins configured
as digital I/O.
Reading this register returns the logic value at the pin, regardless if it is configured as
output or input.
Note: Port 2 consists of 2 bits (P2.0-P2.1) on QSOP24 devices and 1 bit (P2.0) on QFN20 and SOIC16 packages.
202
Preliminary Rev 0.6