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C8051F850-B-GM Datasheet, PDF (107/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash | |||
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C8051F85x/86x
Notes on Registers, Operands and Addressing Modes:
RnâRegister R0âR7 of the currently selected register bank.
@RiâData RAM location addressed indirectly through R0 or R1.
relâ8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP
and all conditional jumps.
directâ8-bit internal data locationâs address. This could be a direct-access Data RAM location (0x00â0x7F) or
an SFR (0x80â0xFF).
#dataâ8-bit constant
#data16â16-bit constant
bitâDirect-accessed bit in Data RAM or SFR
addr11â11-bit destination address used by ACALL and AJMP. The destination must be within the same 2 kB
page of program memory as the first byte of the following instruction.
addr16â16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the
8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
Preliminary Rev 0.6
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