C8051F850-B-GM Datasheet, PDF (281/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
27.1. Enabling / Resetting the WDT
The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's application
software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The
WDT is enabled and reset as a result of any system reset.
27.2. Disabling the WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates
disabling the WDT:
CLR EA
MOV WDTCN,#0DEh
MOV WDTCN,#0ADh
SETB EA
; disable all interrupts
; disable software watchdog timer
; re-enable interrupts
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored.
Interrupts should be disabled during this procedure to avoid delay between the two writes.
27.3. Disabling the WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the
next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use
the watchdog should write 0xFF to WDTCN in the initialization code.
27.4. Setting the WDT Interval
WDTCN.[2:0] controls the watchdog timeout interval. The interval is given by the following equation, where Tlfosc is
the low-frequency oscillator clock period:
T_LFOSC  4^{WDTCN[2:0] + 3}
This provides a nominal interval range of 0.8 ms to 13.1 s. WDTCN.7 must be logic 0 when setting this interval.
Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads 111b after a system reset.
Preliminary Rev 0.6
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