SI5335 Datasheet, PDF (8/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 4. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Duty Cycle
DC
LVPECL, LVDS,
HCSL, CML
45
—
55
%
Output Clocks (Single-Ended)
CMOS
1
—
200
MHz
Frequency
f_OUT
SSTL, HSTL
1
—
350
MHz
CMOS 20%–80%
Rise/Fall Time
t_R/t_F
2 pF load
—
0.45
0.85
ns
CMOS 20%–80%
Rise/Fall Time
t_R/t_F
15 pF load
—
—
2.0
ns
CMOS
V_OH
Output Voltage⁵
V_OL
CMOS
Output Resistance⁵
4 mA load
4 mA load
VDDO – 0.3
—
—
—
50
V
0.3
V
—

HSTL, SSTL
20%–80%
t_R/t_F
See Figure 16.
—
0.35
—
ns
Rise/Fall Time
HSTL Output Voltage ^VOH VDDO = 1.4 to 1.6 V ^0.5xVDDO+0.3
V_OL
—
V_OH
SSTL-3
0.45xVDDO+0.41
VDDOx = 2.97 to
V_OL
3.63 V
—
—
—
V
—
0.5xVDDO –0.3 V
—
—
V
—
0.45xVDDO–0.41 V
SSTL Output Voltage ^VOH
V_OL
SSTL-2 VDDOx =
2.25 to 2.75 V
0.5xVDDO+0.41
—
—
—
—
V
0.5xVDDO–0.41 V
V_OH
SSTL-18
0.5xVDDO+0.34
—
V
VDDOx = 1.71 to
V_OL
1.98 V
—
—
0.5xVDDO–0.34 V
HSTL, SSTL
Output Resistance
—
50
—

Duty Cycle
DC
45
—
55
%
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"
on page 19.
2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on
pins 1 and 2 faster than 0.3 V/ns.
4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See
"3.10.6. CML Outputs" on page 31.
5. Includes effect of internal series 22  resistor.
8
Rev. 1.4