SI5335 Datasheet, PDF (16/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
2. Typical PCIe System Diagram
Main
Board
FPGA
A
PCIe
Core
PCIe
Link
PCIe
Link
PCIe
Switch
Peripheral
Board
PCIe
Core
FPGA
B
Si5335
Clock
Generator
125MHz
LVDS
100MHz HCSL
25MHz LVPECL
25MHz LVPECL
PCIe
Link
FPGA
C
PCIe
Core
Peripheral
Board
Figure 1. PCI Express Switching Application Example
Figure 1 shows the Si5335 in a PCI Express application using the common clock topology. The Si5335 provides
reference clocks to the three FPGAs, each of which requires a different clock signaling format (LVDS, LVPECL),
I/O voltage (1.8, 2.5, 3.3 V), or frequency (25, 100, 125 MHz). In addition, the Si5335 provides a PCIe compliant,
100 MHz HCSL reference clock to the PCIe switch.
16
Rev. 1.4