SI5335 Datasheet, PDF (7/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 4. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Duty Cycle
DC
(PLL
mode)
DC
(PLL
bypass
mode)
< 1 ns t_R/t_F
< 1 ns t_R/t_F
40
—
60
%
45
—
55
%
Input Capacitance
C_IN
Output Clocks (Differential)
—
3.5
—
pF
Frequency
LVPECL, LVDS, CML
1
f_OUT
HCSL
1
—
350
MHz
—
250
MHz
LVPECL
V_OC
common mode
—
Output Voltage
V_SEPP
peak-to-peak single-
ended swing
0.55
V_DDO–
1.45 V
0.8
—
V
0.96
V_PP
LVDS Output Voltage
(2.5/3.3 V)
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
1.125
0.25
1.2
0.35
1.275
V
0.45
V_PP
LVDS Output
V_OC
common mode
0.8
Voltage (1.8 V)
V_SEPP
peak-to-peak single-
ended swing
0.25
0.875
0.35
0.95
V
0.45
V_PP
V_OC
HCSL Output Voltage
V_SEPP
common mode
peak-to-peak single-
ended swing
0.35
0.575
0.375
0.725
0.400
V
0.85
V_PP
V_OC
Common Mode
—
See Note ⁴
—
V
CML Output Voltage
V_SEPP
Peak-to-Peak Single-
ended Swing
0.67
0.860
1.07
V_PP
20% to 80%
Rise/Fall Time
t_R/t_F
LVPECL, LVDS,
—
HCSL, CML
—
450
ps
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"
on page 19.
2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on
pins 1 and 2 faster than 0.3 V/ns.
4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See
"3.10.6. CML Outputs" on page 31.
5. Includes effect of internal series 22  resistor.
Rev. 1.4
7