SI5335 Datasheet, PDF (1/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
WEB- C USTOMIZABLE, A NY- F REQUENCY, A NY- O UTPUT
QUAD CLOCK GENERATOR/BUFFER
Features
 Low power MultiSynth™ technology  Independent output voltage per driver:
enables independent, any-frequency
1.5, 1.8, 2.5, or 3.3 V
synthesis of four frequencies
 Single supply core with excellent
 Configurable as a clock generator or
PSRR: 1.8, 2.5, 3.3 V
clock buffer device
 Up to five user-assignable pin
 Three independent, user-assignable, pin- functions simplify system design:
selectable device configurations
SSENB (spread spectrum control),
 Highly-configurable output drivers with
RESET, Master OEB or OEB per pin,
up to four differential outputs, eight
and Frequency plan select
single-ended clock outputs, or a
(FS1, FS0)
combination of both
 Loss of signal alarm
 Low phase jitter of 0.7 ps RMS
 PCIe Gen 1/2/3/4 common clock
 Flexible input reference:
compliant
External crystal: 25 or 27 MHz
 PCIe Gen 3 SRNS Compliant
CMOS input: 10 to 200 MHz
 Two selectable loop bandwidth
SSTL/HSTL input: 10 to 350 MHz
settings: 1.6 MHz or 475 kHz
Differential input: 10 to 350 MHz
 Independently configurable outputs
support any frequency or format:
LVPECL/LVDS/CML: 1 to 350 MHz
HCSL: 1 to 250 MHz
CMOS: 1 to 200 MHz
SSTL/HSTL: 1 to 350 MHz
 Easy to customize with web-based
utility
 Small size: 4 x 4 mm, 24-QFN
 Low power (core):
45 mA (PLL mode)
12 mA (Buffer mode)
 Wide temperature range: –40 to
+85 °C
Applications
 Ethernet switch/router
 PCI Express Gen 1/2/3/4
 PCIe jitter attenuation
 DSL jitter attenuation
 Broadcast video/audio timing
 Processor and FPGA clocking
 MSAN/DSLAM/PON
 Fibre Channel, SAN
 Telecom line cards
 1 GbE and 10 GbE
Description
The Si5335 is a highly flexible clock generator capable of synthesizing four completely
non-integer-related frequencies up to 350 MHz. The device has four banks of outputs
with each bank supporting one differential pair or two single-ended outputs. Using
Silicon Laboratories' patented MultiSynth fractional divider technology, all outputs are
guaranteed to have 0 ppm frequency synthesis error regardless of configuration,
enabling the replacement of multiple clock ICs and crystal oscillators with a single
device. The Si5335 supports up to three independent, pin-selectable device
configurations, enabling one device to replace three separate clock generators or
buffer ICs. To ease system design, up to five user-assignable and pin-selectable
control pins are provided, supporting PCIe-compliant spread spectrum control, master
and/or individual output enables, frequency plan selection, and device reset. Two
selectable PLL loop bandwidths support jitter attenuation in applications, such as PCIe
and DSL. Through its flexible ClockBuilder™ (www.silabs.com/ClockBuilder) web
configuration utility, factory-customized, pin-controlled devices are available in two
weeks without minimum order quantity restrictions. Measuring PCIe clock jitter is quick
and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
Ordering Information:
See page 41.
Pin Assignments
Top View
24 23 22 21 20 19
XA/CLKIN 1
18 CLK1A
XB/CLKINB 2
17 CLK1B
P3 3
GND 4
GPGNaNdDD
16 VDDO1
15 VDDO2
P5 5
14 CLK2A
P6 ⁶
13 _CLK2B
7 8 9 10 11 12
Rev. 1.4 12/15
Copyright © 2015 by Silicon Laboratories
Si5335