SI5335 Datasheet, PDF (17/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

3. Functional Description
Si5335
XA / CLKIN
XB / CLKINB
P1
P2
P3
P5
P6
LOS
Osc
CLKIN
Programmable
Pin Function
Options:
OEB0/1/2/3
OEB_all
SSENB
FS[1:0]
RESET
PLL Bypass
PLL
Control
÷MultiSynth0
PLL Bypass OEB0
÷MultiSynth1
PLL Bypass ^OEB1
÷MultiSynth2
PLL Bypass ^OEB2
÷MultiSynth3
OEB3
VDDO0
CLK0A
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
Figure 2. Si5335 Functional Block Diagram
3.1. Overview
The Si5335 is a high-performance, low-jitter clock generator or buffer capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz. The device supports free-run operation using an external 25
or 27 MHz crystal, or it can lock to an external clock for generating synchronous clocks. The output drivers support
four differential clocks or eight single-ended clocks or a combination of both. The output drivers are configurable to
support common signal formats, such as LVPECL, LVDS, HCSL, CML, CMOS, HSTL, and SSTL. Separate output
supply pins allow supply voltages of 3.3, 2.5, 1.8, and 1.5 V to support the multi-format output driver. The core
voltage supply accepts 3.3, 2.5, or 1.8 V and is independent from the output supplies. Using its two-stage
synthesis architecture and patented high-resolution MultiSynth technology, the Si5335 can generate four
independent frequencies from a single input frequency. In addition to clock generation, the inputs can bypass the
synthesis stage enabling the Si5335 to be used as a high-performance clock buffer.
Spread spectrum* is available on each of the clock outputs for EMI-sensitive applications, such as PCI Express.
The device includes an interrupt pin that monitors for both loss of PLL lock (LOL) and loss of input signal (LOS)
conditions while configured in clock generator mode. In clock generator mode, the LOS pin is asserted whenever
LOL or LOS is true. In clock buffer mode (i.e., when the PLL is bypassed), the LOS pin is asserted whenever the
input clock is lost. The LOL condition does not apply in clock buffer mode.
*Note: See " Document Change List" on page 46 for more information.
Rev. 1.4
17