SI5335 Datasheet, PDF (12/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 9. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 475 kHz)^1,2
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DSL Random Jitter
(10 kHz–400 kHz)
DSL Random Jitter
(100 kHz–10 MHz)
DSL Random Jitter
(10 Hz–30 MHz)
PCI Express 1.1
Common Clocked
(with spread spectrum)
PCI Express 2.1
Common Clocked
(no spread spectrum)
R_JDSL1
R_JDSL2
R_JDSL3
CLKIN = 70.656 MHz
All CLKn at
—
70.656 MHz⁴
CLKIN = 70.656 MHz
All CLKn at
—
70.656 MHz⁴
CLKIN = 70.656 MHz
All CLKn at
—
70.656 MHz⁴
Total Jitter⁵
—
RMS Jitter⁵, 10 kHz to
1.5 MHz
—
RMS Jitter⁵, 1.5 MHz to
50 MHz
—
0.8
0.9
1.95
20
0.3
0.5
2
ps RMS
2
ps RMS
2.2 ps RMS
34 ps pk-pk
0.5 ps RMS
1.0 ps RMS
PCI Express 3.0
Common Clocked
(no spread spectrum)
PCIe Gen 3 Separate
Reference No Spread,
SRNS
RMS Jitter⁵
PLL BW of 2–4 or
2–5 MHz,
CDR = 10 MHz
—
0.15 0.45 ps RMS
—
0.11
0.32 ps RMS
PCIe Gen 4,
Common Clock
PLL BW of 2–4 or
2–5 MHz,
CDR = 10 MHz
—
0.15 0.45 ps RMS
Period Jitter
J_PER
N = 10,000 cycles⁶
—
10
30 ps pk-pk
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
3. D_J for PCI and GbE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
6. For any output frequency > 5 MHz.
7. Measured in accordance with JEDEC standard 65.
8. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹² rising edges.
9. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
10. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
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Rev. 1.4