SI5335 Datasheet, PDF (25/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
0
1
1
2
For custom Si5335 devices configured to support three frequency plans, the FS1 and FS0 pins should be set as
follows:
FS1
FS0
Profile
0
0
Reserved
0
1
1
1
0
2
1
1
3
If a change is made to the FS pin settings, the device reset pin (RESET) must be held high for the minimum pulse
width specified in Table 3 on page 5 to change the device configuration. The output clocks will be momentarily
squelched until the device begins operation with the new frequency plan.
If the RESET pin is not selected in ClockBuilder as one of the five programmable pins, a power-on reset must be
applied for an FS pin change to take effect.
3.9. Loss-of-Signal Alarm
The Si5335 supports a loss of signal (LOS) output indicator for monitoring the condition of the crystal/clock
reference input. The LOS condition occurs when there is no input clock to the device or the PLL has lost lock (in
clock generator mode). When an input clock is removed, the LOS pin will assert and the output clocks may drift up
to 5% (in clock generator mode). When the input clock with an appropriate frequency is reapplied, the LOS pin will
deassert. In clock buffer mode, LOS is driven high when the input clock is lost.
LOS Output State
0
1
Description
Input clock present and
PLL is locked
Input clock not present and
PLL is not locked
Rev. 1.4
25