SI5335 Datasheet, PDF (39/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Pin # Pin Name
8
LOS
9
CLK3B
10
CLK3A
11
VDDO3
12
P1
13
CLK2B
14
CLK2A
15
VDDO2
16
VDDO1
Table 15. Si5335 Pin Descriptions (Continued)
I/O
O
O
O
VDD
I
O
O
VDD
VDD
Signal Type
Description
Open Drain
Loss of Signal.
A typical pullup resistor of 1–4 k is used on this pin. This pin can
be pulled up to a supply voltage as high as 3.6 V regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, and 24. The LOS
condition allows the pull up resistor to pull the output up to the
supply voltage. See "3.9. Loss-of-Signal Alarm" on page 25.
This pin functions as an input clock loss-of-signal and PLL lock
status pin in clock generator mode:
0 = Input clock present and PLL locked.
1 = Input clock not present or PLL not locked.
In clock buffer mode, LOS is asserted when the input clock is not
present.
Multi
Output Clock B for Channel 3.
May be a single-ended output or half of a differential output with
CLK3A being the other differential half. If unused, leave this pin
floating.
Multi
Output Clock A for Channel 3.
May be a single-ended output or half of a differential output with
CLK3B being the other differential half. If unused, leave this pin
floating.
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A 0.1 µF
capacitor must be located very close to this pin. If CLK3 is not
used, this pin must be tied to VDD (pin 7, 24).
Multi
Multi-Function Input. 3.3 V tolerant.
This pin functions as a multi-function input pin. The pin function
(OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, FS0, FS1, or
RESET) is user-selectable at time of configuration using the Clock-
Builder web configuration utility
Multi
Output Clock B for Channel 2.
May be a single-ended output or half of a differential output with
CLK2A being the other differential half. If unused, leave this pin
floating.
Multi
Output Clock A for Channel 2.
May be a single-ended output or half of a differential output with
CLK2B being the other differential half. If unused, leave this pin
floating.
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B.
A 0.1 µF capacitor must be located very close to this pin. If CLK2 is
not used, this pin must be tied to VDD (pin 7, 24).
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK1A,B.
A 0.1 µF capacitor must be located very close to this pin. If CLK1 is
not used, this pin must be tied to VDD (pin 7, 24).
Rev. 1.4
39