SI5335 Datasheet, PDF (31/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
3.10.5. HCSL Outputs
Host clock signal level (HCSL) outputs are commonly used in PCI Express applications. A typical HCSL driver has
an open source output that requires an external series resistor and a resistor to ground. The Si5335 HCSL driver
has integrated these resistors to simplify the interface to an HCSL receiver. No external components are necessary
when connecting the Si5335 HCSL driver to an HCSL receiver.
3.3, 2.5, or 1.8 V
VDDOx
Rs
50
CLKxA
HCSL
Rs
CLKxB
50
Rt Rt
HCSL
Si5335
Figure 20. Interfacing the Si5335 to an HCSL Receiver
3.10.6. CML Outputs
Current mode logic (CML) is transmitted differentially and terminated to 50  to Vcc as shown in Figure 20. A CML
receiver can be driven with either an LVPECL, CML, or LVDS output. To drive a CML receiver, an Si5335 output
configured in LVPECL or CML mode generates a single-ended output swing of 550 mV to 960 mV. However, to
reduce power consumption by approximately 15 mA per output driver pair (compared to an LVPECL-configured
output), the Si5335's CML output mode can be selected without affecting the output voltage swing. For even lower
power consumption, depending on the input signal swing required, CML receivers can be driven with an Si5335
output configured in LVDS mode. CML output format is not available when the Si5335 is in PLL bypass (clock
buffer) mode.
Driving a CML Receiver Using the LVPECL Output
Si5335
LVPECL
550 mV to 960 mVp-p
50
50
Rb Rb
0.1 µF
0.1 µF
CML
Receiver
50
Vcc
50
Rb = 130 
(2.5 V LVPECL)
Rb = 200 
(3.3 V LVPECL)
Driving a CML Receiver Using the CML or LVDS Output
Si5335
CML or
LVDS
670 mV to 1070 mVp-p (CML)
250 mV to 450 mVp-p (LVDS)
50
50
0.1 µF
0.1 µF
CML
Receiver
50
Vcc
50
Figure 21. Terminating an LVPECL or an LVDS Output to a CML Receiver
Rev. 1.4
31