SI5335 Datasheet, PDF (22/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
3.4.3. Single-Ended CMOS Input Clocks
For synchronous timing applications, the Si5335 can lock to a 10 to 200 MHz CMOS reference clock. A typical
interface circuit is shown in Figure 10. A series termination resistor may be required if the CMOS driver impedance
does not match the trace impedance.
CMOS Input Signal
1.8 V CMOS
R_se = 249 
R_sh = 464 
2.5 V CMOS
R_se = 402 
R_sh = 357 
Keep Rse and Rsh close to
the receiver
0.1 uF
R_se
50
3.3 V CMOS
R_sh
R_se = 499 
R_sh = 274 
0.1 uF
Si5335
Pin 1
Pin 2
Figure 10. Interfacing CMOS Reference Clocks to the Si5335
3.4.4. Single-Ended SSTL and HSTL Input Clocks
HSTL and SSTL single-ended inputs can be input to the differential inputs, pins 1 and 2, of the Si5335 with the
circuit shown in Figure 11.
Some drivers may require a series 25  resistor. If the SSTL/HSTL input is being driven by another Si5335 device,
the 25  series resistor is not required as this is integrated on-chip. The maximum recommended input frequency
in this case is 350 MHz.
Keep termination close to
input pin of the Si5335
V_TT
0.4 to 1.2 V pk-pk
50
0.1 uF
Si5335
50
V_DD
Differential
Input
Pin 1
Pin 2
R₁
0.1 uF
V_TT
0.1 uF
R₂
SSTL_2, SSTL_18, HSTL
R₁ = 2.43 k
R₂ = 2 k
SSTL_3
R₁ = 2.43 k
R₂ = 2 k
Figure 11. Single-Ended SSTL/HSTL Input Clocks to the Si5335
22
Rev. 1.4