SI5335 Datasheet, PDF (38/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
10. Pin Descriptions
Top View
24 23 22 21 20 19
XA/CLKIN 1
18 CLK1A
XB/CLKINB 2
17 _CLK1B
P3 3
GND 4
GPGNaNdDD
16 VDDO1
15 VDDO2
P5 ⁵
14 CLK2A
P6 ⁶
13 _CLK2B
7 8 9 10 11 12
Note: Center pad must be tied to GND for normal operation.
Table 15. Si5335 Pin Descriptions
Pin # Pin Name
1,2
XA/CLKIN,
XB/CLKINB
3
P3
4
GND
5,6
P5, P6
7
VDD
I/O
I
I
GND
I
VDD
Signal Type
Description
Multi
XA/CLKIN, XB/CLKINB.
These pins are used as the main differential or single-ended clock
input or as the XTAL input. See "3.4. Input Configuration" on page
19 and Figures 10, 11, and 12 for connection details. Clock inputs
to these pins must be ac-coupled. Keep the traces from pins 1,2 to
the crystal as short as possible and keep other signals and radiat-
ing sources away from the crystal. The single-ended input voltage
swing must be limited to 1.2 Vpp.
Multi
GND
Multi
Multi-Function Input. 3.3 V tolerant.
This pin functions as a multi-function input pin. The pin function
(OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, or RESET) is
user-selectable at time of configuration using the ClockBuilder web
configuration utility.
Ground.
Must be connected to system ground for proper device operation.
Multi-Function Input.
These pins function as multi-function input pins. The pin functions
(OEB_all, OEB0, OEB1, OEB2, OEB3, or SSENB) are user-
selectable at time of configuration using the ClockBuilder configu-
ration utility. A resistor voltage divider is required when driven by a
signal greater than 1.2 V. See "3.6.1. P5 and P6 Input Control" on
page 24 for details.
Supply
Core Supply Voltage.
This is the core supply voltage, which can operate from a 1.8, 2.5,
or 3.3 V supply. A 0.1 µF bypass capacitor should be located very
close to this pin.
38
Rev. 1.4