SI5335 Datasheet, PDF (34/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
6. Jitter Performance
The Si5335 provides consistently low jitter for any combination of output frequencies. The device leverages a low
phase noise single PLL architecture and Silicon Laboratories’ patented MultiSynth fractional output divider
technology to deliver period jitter of 10 ps pk-pk (typ). The Si5335 provides superior performance to conventional
multi-PLL solutions which may suffer from degraded jitter performance depending on frequency plan and the
number of active PLLs.
7. Power Supply Considerations
The Si5335 has 2 core supply voltage pins (V_DD) and 4 clock output bank supply voltage pins (V_DDO0–V_DDO3),
enabling the device to be used in mixed supply applications. The Si5335 does not typically require ferrite beads for
power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power
supply noise on output jitter. Figure 24 shows that the additive jitter created when a significant amount of noise is
applied to the device power supply is very low.
10
9
8
7
6
5
4
3
2
1
0
0.0001
0.001
0.01
VDDO
VDD
0.1
1
Modulation Frequency (MHz)
Figure 24. Peak-to-Peak Additive Jitter from 100 mV Sine Wave on Supply
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Rev. 1.4