SI5335 Datasheet, PDF (10/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)^1,2,3
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
GbE Random Jitter
(12 kHz–20 MHz)⁴
GbE Random Jitter
(1.875–20 MHz)
OC-12 Random Jitter
(12 kHz–5 MHz)
PCI Express 1.1 Common
Clocked (with spread
spectrum)
PCI Express 2.1 Common
Clocked (no spread spec-
trum)
J_GbE
R_JGbE
J_OC12
CLKIN = 25 MHz
All CLKn at 125 MHz⁵
—
CLKIN = 25 MHz
All CLKn at 125 MHz⁵
—
CLKIN = 19.44 MHz
All CLKn at
—
155.52 MHz⁵
Total Jitter⁶
—
RMS Jitter⁶, 10 kHz to
1.5 MHz
—
RMS Jitter⁶, 1.5 MHz to
50 MHz
—
0.7
1
ps RMS
0.38 0.79 ps RMS
0.7
1
ps RMS
20.1 33.6 ps pk-pk
0.15 1.47 ps RMS
0.58 0.75 ps RMS
PCI Express 3.0 Common
Clocked (no spread
spectrum)
PCIe Gen 3 Separate
Reference No Spread,
SRNS
RMS Jitter⁶
—
0.15 0.45 ps RMS
PLL BW of 2–4 or
2–5 MHz,
—
0.11
0.32 ps RMS
CDR = 10 MHz
PCIe Gen 4,
Common Clock
PLL BW of 2–4 or
2–5 MHz,
—
0.15 0.45 ps RMS
CDR = 10 MHz
Period Jitter
J_PER
N = 10,000 cycles⁷
—
10
30 ps pk-pk
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the
differential clock input slew rates greater than 0.3 V/ns.
4. D_J for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
7. For any output frequency > 10 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹² rising edges.
10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
11. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
10
Rev. 1.4