SI5335 Datasheet, PDF (35/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
8. Loop Bandwidth Considerations
For synchronous reference clock applications, two user-selectable loop bandwidth settings (1.6 MHz and 475 kHz)
are available to allow designers to optimize their timing system to support jitter attenuation of the reference clock.
In general, the 1.6 MHz setting provides the lowest output jitter and should be selected for most applications. The
1.6 MHz option provides faster PLL tracking of the input clock but less jitter attenuation of the input clock than the
475 kHz loop bandwidth option. The 1.6 MHz loop bandwidth option must be selected for all applications which use
a crystal reference input on the XA/XB pins (pins 1 and 2) and for all applications which provide a low jitter input
clock reference to the Si5335.
The 475 kHz setting reduces the clock generator's loop bandwidth, which has the benefit of attenuating some of
jitter that would normally pass through the 1.6 MHz setting. As the PLL loop bandwidth decreases, the intrinsic jitter
of the device increases and is reflected in higher jitter generation specifications, but total output jitter is the best
measure of system performance. Total output jitter includes both the generated jitter as well as the transferred jitter.
This lower loop bandwidth option can be useful in some applications, such as PCIe, DSL or other systems which
may utilize backplane distributed reference clocks. In these systems, the input clock may have appreciable low
frequency jitter (e.g., < 1.6 MHz). The source of the reference clock jitter can arise from suboptimal PCB trace
layouts, impedance mismatches and connectors. Input clock jitter may also be generated from an IC which has
poor power supply rejection performance, resulting in switching power supply noise and jitter coupling onto the
clock input of the Si5335. In these applications, designers may opt to use the 475 kHz loop bandwidth to help
attenuate the input clock jitter. Proper selection of PLL loop bandwidth involves a number of application-specific
considerations. Refer to “AN513: Jitter Attenuation—Choosing the Right Phase-Locked Loop Bandwidth” for more
information.
Please also refer to “AN624: Si5335 Solves Timing Challenges in PCI Express, Computing, Communications and
FPGA-Based Systems”.
Rev. 1.4
35