SI5335 Datasheet, PDF (19/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
3.4. Input Configuration
The Si5335 input can be driven from either an external crystal or a reference clock. Reference selection is made
when the device configuration is specified using the ClockBuilder™ web-based utility available at www.silabs.com/
ClockBuilder.
3.4.1. Crystal Input
If the crystal input option is used, the Si5335 operates as a free-running clock generator. In this mode of operation
the device requires a low-cost 25 or 27 MHz fundamental mode crystal connected across XA and XB as shown in
Figure 4. Given the Si5335’s frequency flexibility, the same 25 or 27 MHz crystal can be reused to generate any
combination of output frequencies. Custom frequency crystals are not required. The Si5335 integrates the crystal
load capacitors on-chip to reduce external component count. The crystal should be placed very close to the device
to minimize stray capacitance. To ensure stable oscillation, the recommended crystal specifications provided in
Tables 6 and 7 must be followed. See AN360 for additional details regarding crystal recommendations.
XTAL
Si5335
XA/CLKIN
XB/CLKINB
Figure 4. Connecting an XTAL to the Si5335
3.4.2. Differential Input Clocks
The multi-format differential clock inputs of the Si5335 will interface with today’s most common differential signals,
such as LVDS, LVPECL, CML, and HCSL. The differential inputs are internally self-biased and must be ac-coupled
externally with a 0.1 µF capacitor. The receiver will accept a signal with a voltage swing between 400 mV and
2.4 V_PP differential. Each half of the differential signal must not exceed 1.2 V_PP at the input to the Si5335 or else
the 1.3 V dc voltage limit may be exceeded.
3.4.2.1. LVDS Inputs
When interfacing the Si5335 device to an LVDS signal, a 100  termination is required at the input along with the
required dc blocking capacitors as shown in Figure 5.
LVDS
Keep termination close to
input pin of the Si5335
50
50
Must be ac coupled
0.1 uF
100
0.1 uF
Si5335
Pin 1
Pin 2
Figure 5. LVDS Input Signal
3.4.2.2. LVPECL Input Clocks
Recommended configurations for interfacing an LVPECL input signal to the Si5335 are shown in Figure 6. Typical
values for the bias resistors (Rb) range between 120 and 200  depending on the LVPECL driver. The 100 
resistor provides line termination. Because the receiver is internally self-biased, no additional external bias is
required.
Another solution is to terminate the LVPECL driver with a Thevenin configuration as shown in Figure 6b. The
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