SI5335 Datasheet, PDF (32/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
4. Power Consumption
In clock generator mode, the Si5335 Power consumption is a function of the following:
 Supply voltage
 Frequency of output Clocks
 Number of output Clocks
 Format of output Clocks
Because of internal voltage regulation, the current from the core V_DD is independent of the V_DD voltage and hence
the plot shown in Figure 5 can be used to estimate the V_DD core (pins 7 and 24) current.
The current from the output supply voltages can be estimated from the values provided in Table 2, “DC
Characteristics,” on page 4. To get the most accurate value for V_DD currents, the Si5338-EVB with ClockBuilder
Desktop software should be used.
To do this, go to the “Power” tab of ClockBuilder Desktop and press “Measure”. In this manner, a specific
configuration can be implemented on the EVB and the actual current for each supply voltage measured. When
doing this it is critical that the output drivers have the proper load impedance for the selected format.
When testing for output driver current with HSTL and SSTL, it is required to have load circuitry as shown in "3.10.2.
SSTL and HSTL Outputs" on page 27. The Si5338 EVB has layout pads that can be used for this purpose. When
testing for output driver current with LVPECL the same layout pads can be used to implement the LVPECL bias
resistor of 130  (2.5 V VDDx) or 200  (3.3 V VDDx). See the schematic in the Si5338-EVB data sheet and
AN408 for additional information.
80
75
4 Active Outputs, Fractional Output MS
4 Active Outputs, Integer Output MS
70
3 Active Outputs, Fractional Output MS
3 Active Outputs, Integer Output MS
2 Active Outputs, Fractional Output MS
65
2 Active Outputs, Integer Output MS
1 Active Output, Fractional Output MS
60
1 Active Output, Integer Output MS
55
50
45
40
35
30
0
50
100
150
200
250
300
350
400
Output Frequency (MHz)
Figure 22. Core VDD Supply Average Current vs Output Frequency
32
Rev. 1.4