SI5335 Datasheet, PDF (46/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 0.9
 Updated Table 2, “DC Characteristics,” on page 4.
Added core power supply specification in buffer mode.
 Updated Table 3, “Performance Characteristics,” on
page 5.
Added T_RESET specification.
 Updated Table 4, “Input and Output Clock
Characteristics,” on page 6.
Corrected V_I on pin 1 to 1.3 V (max).
Updated CML output voltage specification to 0.86 Vpp.
 Updated Table 6, “Crystal Specifications for
25 MHz,” on page 9.
Corrected CL to 18 pF (typical).
 Updated Table 7, “Crystal Specifications for
27 MHz,” on page 9.
Corrected CL to 18 pF (typical).
 Updated "3.4. Input Configuration" on page 19.
Revised text in Section 3.4.2.
 Updated "3.6.1. P5 and P6 Input Control" on page
24.
Added Figure 13 to replace Table 15.
 Updated Figure 21 on page 31.
 Updated Table 14 on page 23.
Corrected Assignable Pin Name column entries.
 Updated "3.10. Output Stage" on page 26.
Revised throughout and included termination circuit
diagrams and text.
 Removed references to P4 as a programmable pin
option throughout document. Pin 4 is now a ground
pin.
Revision 0.9 to Revision 1.0
 Updated Table 9 on page 12.
DSL random jitter from 2.1 ps RMS (typ) to 1.95 ps RMS
(typ) and from "—" (max) to 2.2 ps RMS (max).
 Corrected text in “9.2. Synchronous Frequency
Translation” to match the capabilities of the
ClockBuilder web utility.
Revision 1.0 to Revision 1.1
 Updated Table 8 on page 10 and Table 9 on
page 12.
Updated typical specifications for total jitter for PCI
Express 1.1 Common clocked topology.
Updated typical specifications for RMS jitter for PCI
Express 2.1 Common clocked topology.
 Updated Table 10 on page 14.
Updated typical additive jitter (12 kHz–20MHz) from
0.150 to 0.165 ps RMS.
 Added " Document Change List" on page 46.
Revision 1.1 to Revision 1.2
 Removed down spread spectrum errata that has
been corrected in revision B.
 Updated ordering information to refer to revision B
silicon.
 Updated top marking explanation in Section 14.2.
Revision 1.2 to Revision 1.3
 Added link to errata document.
Revision 1.3 to Revision 1.4
 Updated Features on page 1.
 Updated Description on page 1.
 Updated specs in Table 8.
 Updated specs in Table 9.
46
Rev. 1.4