SI5335 Datasheet, PDF (18/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
3.2. MultiSynth Technology
Next-generation timing architectures require a wide range of frequencies which are often non-integer related.
Traditional clock architectures address this by using a combination of single PLL ICs, 4-PLL ICs and discrete XOs,
often at the expense of BOM complexity and power. The Si5335 uses patented MultiSynth technology to
dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops
(PLLs) in a single device, greatly minimizing size and power requirements versus traditional solutions. Based on a
fractional-N PLL, the heart of the architecture is a low phase noise, high-frequency VCO. The VCO supplies a high
frequency output clock to the MultiSynth block on each of the four independent output paths. Each MultiSynth
operates as a high-speed fractional divider with Silicon Laboratories' proprietary phase error correction to divide
down the VCO clock to the required output frequency with very low jitter.
The first stage of the MultiSynth architecture is a fractional-N divider which switches seamlessly between the two
closest integer divider values to produce the exact output clock frequency with 0 ppm error. To eliminate phase
error generated by this process, MultiSynth calculates the relative phase difference between the clock produced by
the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock
waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter
performance. Based on this architecture, the output of each MultiSynth can produce any frequency from 1 to
350 MHz.
MultiSynth
Fractional-N
f_VCO
Divider
Phase
Adjust
f_OUT
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
Figure 3. Silicon Labs' MultiSynth Technology
3.3. ClockBuilder Web-Customization Utility
ClockBuilder is a web-based utility available at www.silabs.com/ClockBuilder that allows hardware designers to
tailor the Si5335’s flexible clock architecture to meet any application-specific requirements and order custom clock
samples. Through a simple point-and-click interface, users can specify any combination of input frequency and
output frequencies and generate a custom part number for each application-specific configuration. There are no
minimum order quantity restrictions.
ClockBuilder enables mass customization of clock generators. This allows a broader range of applications to take
advantage of using application-specific pin controlled clocks, simplifying design while eliminating the firmware
development required by traditional I²C-programmable clock generators.
Based on Silicon Labs’ patented MultiSynth technology, the device PLL output frequency is constant and all clock
output frequencies are synthesized by the four MultiSynth fractional dividers. All PLL parameters, including divider
settings, VCO frequency, loop bandwidth, charge pump current, and phase margin are internally set by the device
during the configuration process. This ensures optimized jitter performance and loop stability while simplifying
design.
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Rev. 1.4