SI5335 Datasheet, PDF (26/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
3.10. Output Stage
The output stage consists of programmable output drivers as shown in Figure 14.
Output
Stage
VDDO0
CLK0A
CLK0B
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
Figure 14. Output Stage
The Si5335 devices provide four outputs that can be differential or single-ended. When configured as single-
ended, the driver generates two signals that can be configured as in-phase or complementary. Each of the outputs
has its own output supply pin, allowing the device to be used in mixed supply applications without the need for
external level translators. The CML output driver generates a similar output swing as the LVPECL driver but
consumes half the current. CML outputs must be ac-coupled.
3.10.1. CMOS/LVTTL Outputs
The CMOS output driver has a controlled impedance of about 50 , which includes an internal series resistor of
approximately 22 . For this reason, an external Rs series resistor is not recommended when driving 50  traces.
If the trace impedance is higher than 50 , a series resistor, Rs, should be used. A typical configuration is shown in
Figure 15. A CMOS output driver can be configured with ClockBuilder as a single- or dual-output driver. Dual
otuput configurations support in-phase or complementary outputs. The output supports 3.3, 2.5, and 1.8 V CMOS
signal levels when the appropriate voltage is supplied to the external VDDO pin and the device is configured
accordingly.
Si5335
3.3, 2.5, or 1.8 V
V_DDOx
CMOS
CLKxA
CLKxB
LVTTL/
CMOS
50
50
Figure 15. Interfacing to a CMOS Receiver
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Rev. 1.4