SI5335 Datasheet, PDF (24/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 14. Multi-Function Control Inputs (Continued)
FS0
FS1
RESET
SSENB
Frequency Select.
Selects active device frequency plan from factory-configured
profiles. See “3.8. Frequency Select/Device Reset” for more
information.
Frequency Select.
Selects active device frequency plan from factory-configured
profiles. See “3.8. Frequency Select/Device Reset” for more
information.
Reset.
Asserting this pin (driving high) is required to change
FS1,FS0 pin setting. Reset is not required if FS1,FS0 pins are
unassigned.
Spread Spectrum Enable.
Enables PCI-compliant spread spectrum clocking on all 100
MHz clock outputs when low.
P1
P1 (for 2-plan devices)
P2 (for 3-plan devices)
P1, P2, P3
P1, P2, P3, P5*, P6*
*Note: See “3.6.1. P5 and P6 Input Control” for recommended termination circuits for these pins.
3.6.1. P5 and P6 Input Control
Control input signals to P5 and P6 cannot exceed 1.2 V. When these inputs are driven from CMOS sources, a
resistive attenuator is required for pins 5 and 6, as shown in Figure 13.
CMOS input signal
Keep Rse and Rsh close to pin 5 and pin 6
Rse
50
Rsh
Si5335
Pin 5, Pin 6
1.8 V CMOS
R_se = 1 k
R_sh = 1.58 k
2.5 V CMOS
1.96 k
1.58 k
3.3 V CMOS
3.09 k
1.58 k
Figure 13. P5, P6 Control Pin Termination
3.7. Output Enable
Each of the device’s four banks of clock outputs can be individually disabled using OEB0, OEB1, OEB2 and OEB3,
respectively. Alternatively, all clock outputs can be disabled using the master output enable OEB_all. When a
Si5335 clock output bank is disabled, the output disable state is determined by the configuration specified in the
ClockBuilder web utility. When one or more banks of clock outputs are enabled or disabled, clock start and stop
transitions are handled glitchlessly.
3.8. Frequency Select/Device Reset
The device frequency plan is customized using the ClockBuilder web utility. The Si5335 optionally supports up to
three unique, pin-selectable configurations per device, enabling one device to replace up to three separate clock
ICs. To select a particular frequency plan, set the FS pins as outlined below:
For custom Si5335 devices configured to support two frequency plans, the FS1 pin should be set as follows:
FS1
Profile
24
Rev. 1.4