SI5335 Datasheet, PDF (6/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 4. Input and Output Clock Characteristics
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Input Clock (AC Coupled Differential Input Clocks on Pins 1 and 2)¹
Frequency
f_IN
LVDS, LVPECL,
10²
—
HCSL, CML
350
MHz
Differential Voltage
V_PP
350 MHz input
0.4
Swing
Rise/Fall Time³
t_R/t_F
20%–80%
—
DC
(PLL
< 1 ns t_R/t_F
40
mode)
Duty Cycle³
DC
(PLL
bypass
< 1 ns t_R/t_F
45
mode)
Input Impedance¹
R_IN
10
Input Capacitance
C_IN
—
Input Clock (AC-Coupled Single-Ended Input Clock on Pin 1)
Frequency
f_IN CMOS, HSTL, SSTL
10²
CMOS Input Voltage
Swing
V_I
200 MHz
0.8
—
2.4
V_PP
—
1.0
ns
—
60
%
—
55
%
—
—
k
3.5
—
pF
—
200
MHz
—
1.2
Vpp
CMOS Rise/Fall Time t_R/t_F
CMOS Rise/Fall Time t_R/t_F
HSTL/SSTL Input
Voltage
V_I(HSTL/
SSTL)
HSTL/SSTL Rise/Fall
Time
t_R/t_F
10%–90%
20%–80%
200 MHz
10%–90%
—
—
4
ns
—
—
2.3
ns
0.4
—
1.2
V_PP
—
—
1.4
ns
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"
on page 19.
2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on
pins 1 and 2 faster than 0.3 V/ns.
4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See
"3.10.6. CML Outputs" on page 31.
5. Includes effect of internal series 22  resistor.
6
Rev. 1.4