SI5335 Datasheet, PDF (5/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 3. Performance Characteristics
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
PLL Acquisition Time
PLL Tracking Range
t_ACQ
f_TRACK
1.6 MHz loop bandwidth
475 kHz or 1.6 MHz loop
bandwidth
PLL Loop Bandwidth
MultiSynth Frequency
Synthesis Resolution
f_BW1
f_BW2
f_RES
High bandwidth option
Low bandwidth option
Output frequency < Fvco/8
CLKIN Loss of Signal Detect
t_LOS
Time
CLKIN Loss of Signal Release
Time
t_LOSRLS
POR to Output Clock Valid
t_RDY
Input-to-Output Propagation
Delay
t_PROP
Buffer Mode
(PLL Bypass)
Reset Minimum Pulse Width
Output-Output Skew¹
Spread Spectrum PP
Frequency Deviation²
t_RESET
t_DSKEW
SS_DEV
F_OUT > 5 MHz
F_OUT = 100 MHz
Spread Spectrum Modulation
Rate³
SS_DEV
F_OUT = 100 MHz
Notes:
1. Outputs at integer-related frequencies and using the same driver format.
2. Default value is 0.5% down spread.
3. Default value is 31.5 kHz for PCI compliance.
Min Typ
—
—
5000 20000
—
1.6
—
475
0
0
—
2.6
0.01 0.2
—
—
—
2.5
—
—
—
—
— –0.45
30 31.5
Max
25
—
—
—
1
5
1
2
4
200
100
–0.5
33
Unit
ms
ppm
MHz
kHz
ppb
µs
µs
ms
ns
ns
ps
%
kHz
Rev. 1.4
5