SI5335 Datasheet, PDF (27/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
3.10.2. SSTL and HSTL Outputs
The Si5335 supports both SSTL and HSTL outputs, which can be single-ended or differential. The recommended
termination scheme for SSTL is shown in Figure 16. The V_TT supply can be generated using a simple voltage
divider as shown below (note that Rt = 50 ).
Si5335
SSTL (3.3, 2.5, or 1.8 V)
HSTL (1.5 V)
VDDOx
SSTL
CLKxA
50
or
CLKxB
HSTL
50
V_TT V_TT
Rt
Rt
SSTL_3
SSTL_2
SSTL_18
HSTL
V_DDO
R₁
V_TT
SSTL_2, SSTL_18, HSTL
R₁ = 2 k
R₂ = 2 k
SSTL_3
R₁ = 2.43 k
R₂ = 2 k
0.1 µF
R₂
Figure 16. Interfacing the Si5335 to an SSTL or HSTL Receiver
3.10.3. LVPECL Outputs
The LVPECL driver is configurable in both 3.3 V or 2.5 V standard LVPECL modes. The output driver can be ac-
coupled or dc-coupled to the receiver.
3.10.3.1. DC-Coupled LVPECL Outputs
The standard LVPECL driver supports two commonly used dc-coupled configurations. Both of these are shown in
Figure 17a and Figure 17b. LVPECL drivers were designed to be terminated with 50  to VDD–2 V, which is
illustrated in Figure 17a. V_TT can be supplied with a simple voltage divider as shown.
An alternative method of terminating LVPECL is shown in Figure 17b, which is the Thevenin equivalent to the
termination in Figure 17a. It provides a 50  load terminated to V_DD–2.0 V. For 3.3 V LVPECL, use R₁ = 127 and
R₂ = 82.5 ; for 2.5 V LVPECL, use R₁ = 250 and R₂ = 62.5 The only disadvantage to this type of termination
is that the Thevenin circuit consumes additional power from the V_DDO supply.
Rev. 1.4
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