SI5335 Datasheet, PDF (13/47 Pages) Silicon Laboratories – WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER

Si5335
Table 9. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 475 kHz)^1,2 (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Cycle-Cycle Jitter
N = 10,000 cycles
J_CC
Output MultiSynth
—
operated in integer or
9
29
ps pk⁷
fractional mode⁶
Random Jitter
(12 kHz–20 MHz)
Output and feedback
R_J
MultiSynth in integer or ^—
1
2.5 ps RMS
fractional mode⁶
Deterministic Jitter
Output MultiSynth
operated in fractional
—
3
15 ps pk-pk
D_J
mode⁶
Output MultiSynth
operated in integer
—
2
10 ps pk-pk
mode⁶
Total Jitter
(12 kHz–20 MHz)
Output MultiSynth
operated in fractional
—
13
36 ps pk-pk
T_J = D_J+14xR_J ^mode6
(See Note ⁸) _{Output MultiSynth}
operated in integer
—
15
30 ps pk-pk
mode⁶
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
3. D_J for PCI and GbE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
6. For any output frequency > 5 MHz.
7. Measured in accordance with JEDEC standard 65.
8. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹² rising edges.
9. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
10. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.4
13