K4C89363AF Datasheet, PDF (55/58 Pages) Samsung semiconductor – 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

K4C89363AF
Functional Description (Continued)
• Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
Data
Data 0
Data 1
Data 2
Data 3
Access Address
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
Burst Length
2 words
4 words
(R-3) C A S Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of C A S Latency depends on the frequency of CLK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
Addressing sequence for Interleave mode
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
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REV. 0.0 Nov. 2002