K4C89363AF Datasheet, PDF (44/58 Pages) Samsung semiconductor – 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

K4C89363AF
Mode Register Set Timing (CL=4, BL=4)
From Write operation to Mode Register Set operation
CLK
CLK
0
1
2
3
4
5
6
7
8
Command
WRA
LAL
DESL
RDA MRS
9
10
11
12
13
14
15
l_{R C} =7cycles
DESL
RoDrA
LAL
WRA
A14~A0
UA
LA
Valid
(opcode)
UA
LA
BA0, BA1
BA
BA0="0"
BA1="0"
BA
WL + BL/2
Unidirectional DS/QS mode
LDS/UDS
(Input)
LQS/UQS
(Output)
DQ
(Output)
Low
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
LDS/UDS
(Input)
LQS/UQS
(Output)
DQ
(Output)
D0 D1 D2 D3
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
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REV. 0.0 Sep. 2002