K4C89363AF Datasheet, PDF (45/58 Pages) Samsung semiconductor – 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

K4C89363AF
Extended Mode Register Set Timing (CL=4, BL=2)
From Read operation to Extended Mode Register Set operation
CLK
CLK
0
1
2
Command
RDA
LAL
3
4
DESL
5
6
7
8
RDA MRS
9
10
11
12
13
14
15
l_{R C} =7cycles
DESL
RoDrA
LAL
WRA
A14~A0
UA
LA
Valid
(opcode)
UA
LA
BA0, BA1
BA
BA0="0"
BA1="0"
BA
CL + BL/2
Unidirectional DS/QS mode
LDS/UDS
(Input)
LQS/UQS
(Output)
DQ
(Output)
Low
Q0 Q 1
Unidirectional DS/Free Running QS mode
LDS/UDS
(Input)
LQS/UQS
(Output)
DQ
(Output)
Q0 Q 1
Note : Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
When DQ strobe mode is changed by EMRS, QS output is invalid for I_RSC period.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
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REV. 0.0 Sep. 2002