K4C89363AF Datasheet, PDF (23/58 Pages) Samsung semiconductor – 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

K4C89363AF
Timing Diagrams
Single Bank Read Timing (CL=4)
CLK
0
1
2
3
4
5
6
CLK
l_{R C} =5cycles
Command
Address
RDA
LAL
l_{R C D} =1cycle
UA
LA
DESL
l_RAS =4cycles
RDA
LAL
l_{R C D} =1cycle
UA
LA
7
8
9
l_RC =5cycles
DESL
l_RAS =4cycles
10
11
RDA
LAL
l_{R C D}=1cycle
UA
LA
12
13
14
l_{R C} = 5 c y c l e s
DESL
l_{R A S}=4cycles
15
RDA
UA
Bank Add.
#0
Unidirectional DS/QS mode
BL =2
LDS/UDS
(Input)
LQS/UQS
(Output)
Low
DQ
(Output)
BL =4
LDS/UDS
(Input)
Hi-Z
CL=4
LQS/UQS
(Output)
DQ
(Output)
Low
Hi-Z
CL=4
Unidirectional DS/Free Running QS mode
BL =2
LDS/UDS
(Input)
LQS/UQS
(Output)
DQ
(Output)
BL =4
LDS/UDS
(Input)
Hi-Z
CL=4
LQS/UQS
(Output)
DQ
(Output)
Hi-Z
CL=4
#0
#0
#0
CL=4
CL=4
Q0 Q 1
Q0 Q 1
Q0
CL=4
CL=4
Q0 Q 1 Q2 Q 3
Q0 Q 1 Q2 Q 3
Q0
CL=4
CL=4
Q0 Q 1
Q0 Q 1
Q0
CL=4
CL=4
Q0 Q 1 Q2 Q 3
Q0 Q 1 Q2 Q 3
Q0
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REV. 0.0 Sep. 2002