PNX17XX Datasheet, PDF (808/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 29: Endian Mode
3. Endian Mode Theory
There are two basic laws of endian mode: one imposed by CPU history, and one by
convention. Both must be met by any system architecture that implements dual-
endian operation capability. In addition, there are some implementation choices for a
system architecture. Section 6. explains the choices that were made for the PNX17xx
Series on-chip buses. These choices are somewhat arbitrary, but they must be
followed to ensure future compatibility.
3.1 Law 1: The “CPU Rule”
This section is intended to explain CPU endian modes in detail. For those familiar
with CPUs and endian modes, it is optional reading.
The following summarizes how CPUs and byte-addressable memory operate:
• When storing an “n byte” size item from a CPU register to memory at address “A,”
the bytes modified are always the bytes with byte address “A”..”A+n-1.”
• In little-endian mode, the byte at address “A” receives the least significant bits of
the multi-byte item.
• In big-endian mode, the byte at address “A” receives the most significant bits.
Consider the following example a (hypothetical) C struct:
struct {
UInt8C;//"command" byte
UInt8F;//"flags" byte
UInt16L;//"length" 16 bit value
UInt32A;//"address" 32 bit value
} DMA_Descriptor;
Remark: This is based on an example in the Apple® publication, ”Designing PCI
Cards and Drivers for Power Macintosh Computers,” Appendix A.
A compiler would assign byte offsets as follows: C:0, F:1, L:2, A:4. This assignment is
independent of system endian mode.
Figure 2 and Figure 3 show the two layout views.
Word 1
0
1
2
Word 2
4
C
F
L
A
Figure 2: Big-Endian Layout of DMA_Descriptor
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
29-4