PNX17XX Datasheet, PDF (252/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 7: PCI-XIO Module
Table 9: Registers Description
Bit Symbol
Acces
s
Value
Description
Offset 0x04 0090
DMA DTL tuning
31:16 Reserved
R
0
15:8 dma_threshold
R/W 0x1B
Threshold for when DMA DTL requests more read data when initial
fetch is less than total dma length.
7:3 Reserved
R
0
2:0 dma_fetch
R/W 010
Encoded DMA DTL read block size
siz read_block_siz
000: 8 bytes
001: 16 bytes
010: 32 bytes
011: 64 bytes
100: 128 bytes
101: 256 bytes
110: 512 bytes
111: 1024 bytes
Offset 0x04 0094—07FC Reserved
Offset 0x04 0800
DMA PCI Address
This register will accept only word writes.
31:0 dma_eaddr
R/W 1C00_00 This is the external starting address for the DMA engine. It is used
00
for DMA transfers over PCI and XIO. Bit 0 and 1 are not used
because all DMA transfers are word aligned.
Offset 0x04 0804
DMA Internal Address
This register will accept only word writes.
31:0 dma_iaddr
R/W 0010_00 This is the internal read source/ write destination address in
00
SDRAM.
Offset 0x04 0808
DMA Transfer Size
This register will accept any size writes.
31:16 Reserved
R/W 0
15:0 dma_length
R/W 800
This is the length of the DMA transfer (number of 4-byte words).
Offset 0x04 080C
DMA Controls
This register will accept any size writes.
31:11 Reserved
R
0
10 single_data_phase
R/W 0
1 = Limit DMA to single data phase transactions.
This overrides “max_burst_size.”
0 = Use max_burst_size to determine burst size.
9
snd2xio
R/W 0
0 = DMA will target PCI.
1 = DMA will target XIO.
8
fix_addr
R/W 0
0 = DMA will use linear address.
1 = DMA will use a fixed address.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
7-31