PNX17XX Datasheet, PDF (352/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 10: LCD Controller
3. Operation
Similar power sequence applies for the power down sequence, resulting in the
defined t4 and t5 parameters.
After a power down sequence is completed, a minimum time, t6, is necessary before
the next power up sequence can be started.
These delay values, t2, t3, t4, t5, and t6, are programmable in the LCD controller.
3.1 Overview
After reset, an initialization program (like an LCD driver) sets up the values in the
LCD_SETUP register. This register is used to enable the LCD interface and to specify
the power sequencing delay values needed for the particular LCD panel. Refer to
Section 4. on page 10-6 for the MMIO register layout details. This register is
implemented as a ‘write once’ register to prevent a software application from
changing the delay values after the initialization program has set the correct values.
Programming incorrect values may damage the LCD panel.
When the software is ready to send data to the LCD panel, it sets START_PUD_SEQ
bit in the LCD_CONTROL register. This starts the power up sequencing. Similarly,
when the software wants to shut down the LCD panel, it resets the bit. This starts the
power down sequencing.
The power sequencing is controlled by a state machine to guaranty all the critical
timing parameters.
3.2 Power Sequencing State Machine
The state machine in the LCD controller generates the control signals to gate the
data/control signals for the LCD interface. On reset these signals are de-asserted so
that the LCD interface is disabled. Once the power up sequence is started, these
signals are asserted in the order required for the power up sequence. The delays are
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
10-3