PNX17XX Datasheet, PDF (192/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 5: The Clock Module
Table 11: CLOCK MODULE REGISTERS …Continued
Bit Symbol
Acces
s
Value
Description
2:1 sel_clk_lan
R/W 00
00: clk_lan = 27 MHz xtal_clk
01: clk_lan = clk_lan_src
10: clk_lan = 27 MHz xtal_clk
11: clk_lan = AO_SD[0]
0
en_clk_lan
R/W 1
1: enable clk_lan
Offset 0x04,711C
31:4 Reserved
3
turn_off_ack
CLK_LAN_RX_CTL
R/W -
R
0
2:1 sel_clk_lan_rx
R/W 00
0
en_clk_lan_rx
Offset 0x04,7120
31:4 Reserved
R/W 1
CLK_LAN_TX_CTL
R/W -
3
turn_off_ack
R
0
2:1 sel_clk_lan_tx
R/W 00
0
en_clk_lan_tx
Offset 0x04,7124
31:4 Reserved
R/W 1
CLK_IIC_CTL
R/W -
3
turn_off_ack
R
0
2:1 sel_clk_iic
R/W 00
0
en_clk_iic
Offset 0x04,7128
31:7 Reserved
R/W 1
CLK_DVDD_CTL
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_lan_rx = 27 MHz xtal_clk
01: clk_lan_rx = CLK_LAN_RX pin
10: clk_lan_rx = 27 MHz xtal_clk
11: clk_lan_rx = CLK_LAN_RX pin
1: enable clk_lan_rx
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_lan_tx = 27 MHz xtal_clk
01: clk_lan_tx = CLK_LAN_TX pin
10: clk_lan_tx = 27 MHz xtal_clk)
11: clk_lan_tx = CLK_LAN_TX pin
1: enable clk_lan_tx
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_iic_tx = 27 MHz xtal_clk
01: clk_iic_tx = clk_24
10: clk_iic_tx = 27 MHz xtal_clk
11: clk_iic_tx = AO_SD[1]
1: enable clk_iic
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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