PNX17XX Datasheet, PDF (278/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 8: General Purpose Input Output Pins
• An overrun error interrupt is generated whenever new data is received before the
DATA_VALID interrupt has been cleared. The old data is not overwritten, the new
data is lost. The overrun interrupt shares the same interrupt MMIO registers as
the VALID_DATA interrupt. The interrupt is enabled with INT_ENABLE4, cleared
through INT_CLEAR4 and consulted through INT_STATUS4 MMIO registers.
• Upon a DATA_VALID interrupt the corresponding 32-bit TimeStamp Unit (TSU)
MMIO register is stable to be read by software when the relevant
DATA_VALID_[11:0] flag in the INT_STATUS4 MMIO register is raised. The TSU
register contains the timestamp information, a direction bit and a 31-bit
timestamp value, see Section 2.2.2.
Event monitoring is commonly used for low frequency events (less than a 100 per
second) while signal monitoring can be used for more frequent events. Therefore the
timestamp units are shared with the Signal Monitoring logic, Section 2.3.1.
2.2.1 Timestamp Reference clock
The timestamp reference clock is based on a 34-bit counter running at 108 MHz.
However the frequency used for all timestamping in PNX17xx Series is 13.5 MHz
(i.e., 108 MHz/8) which gives a better than 75 ns event resolution, i.e. only the upper
32-bit of the counter is visible by software. The counter can be observed with the
TIME_CTR MMIO register.
The counter is reset by the PNX17xx Series system reset.
2.2.2 Timestamp format
Any change (according to the monitored edge event) generates a 31-bit timestamp
and a 1 bit edge direction in a 32-bit word. The 1-bit direction indicator is a logic ‘1’ if
a rising edge has occurred and a logic ‘0’ if a falling edge has occurred. The direction
bit is the MSB of the 32-bit word generated. This is pictured in Figure 3.
31 30
0
Dir
31-bit timestamp
Dir = 0 => falling edge
Dir = 1 => rising edge
Figure 3: 32-bit Timestamp Format
Remark: The event timestamps can be written (per monitored signal) to a memory
buffer, Section 2.3.1, or to a timestamp unit register, which is software readable.
2.3 GPIO: The Signal Monitoring & Pattern Generation Modes
There are 4 FIFO queues available to perform signal monitoring or pattern generation
(mutually exclusive). Each FIFO queue can be programmed to operate in either of
these modes for a selected group of GPIO pins.
The FIFO has DMA capability to allow efficient CPU access to large event lists (in
opposite to the event monitoring described in Section 2.2).
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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