PNX17XX Datasheet, PDF (196/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 5: The Clock Module
Table 11: CLOCK MODULE REGISTERS …Continued
Bit Symbol
Acces
s
Value
Description
3
vip_output_enable_n R/W 1
VIP output enable
0: output, the clock is generated internally
1: input, the clock is provided by an external source unless
sel_clk_vip is 00 then it is still the xtal clock.
2:1 sel_clk_vip
R/W 00
00: clk_vip = 27 MHz xtal_clk (overrides vip_output_enable_n).
The following is only valid when vip_output_enable_n is 0.
01: clk_vip = DDS7
10: clk_vip = DDS7
11: clk_vip = XIO_D[11]
0
en_clk_vip
R/W 1
1: enable clk_vip
Offset 0x04,7214
CLK_VLD_CTL
31:7 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
5:3 sel_clk_vld_src
R/W 000
000: clk_vld_src = clk_144
001: clk_vld_src = clk_123
010: clk_vld_src = clk_108
011: clk_vld_src = clk_96
100: clk_vld_src = clk_86
101: clk_vld_src = clk_78
110: clk_vld_src = clk_72
111: clk_vld_src = clk_66
2:1 sel_clk_vld
R/W 00
00: clk_vld = 27 MHz xtal_clk
01: clk_vld = clk_vld_src
10: clk_vld = 27 MHz xtal_clk
11: clk_vld = XIO_D[12]
0
en_clk_vld
R/W 1
1: enable clk_vld
Offset 0x04,7300
AI_OSCLK_CTL
31:4 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1 sel_ai_osclk
R/W 00
00: ai_osclk = 27 MHz xtal_clk
01: ai_osclk = DDS4
10: ai_osclk = 27 MHz xtal_clk
11: ai_osclk = XIO_D[13]
0
en_ai_osclk
R/W 1
1: enable clk_ai_osclk
Offset 0x04,7304
CLK_AI_SCK_CTL
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5-45