PNX17XX Datasheet, PDF (337/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 9: DDR Controller
In general, setting the cpu_limit too low will block the CPU too frequently causing a
too high latency (execution time). Setting the cpu_limit too high can completely block
the soft real time DMA for a long time when the hard real time DMA and CPU
bandwidth are peaking. But perhaps the long latency that causes the soft real time
may not be a problem.
3.6 The DDR Controller and the DDR Memory Devices
The DDR SDRAM Controller is compatible with most of the DDR SDRAM vendors.
This is achieved when the correct timing parameters are programmed in the MMIO
registers holdings the timing parameters has presented in the two following sections.
4. Timing Diagrams and Tables
PNX17XX_SER_1
Preliminary data sheet
This section shows how programmable timing parameters direct the operation of the
DDR SDRAM Controller. It is not the intention of this section to give a complete
overview of all DDR interface signaling. Only the main ones are described.
Table 6 presents the values that are used for the different timing parameters in the
timing diagrams.
Table 6: DDR Timing Parameters
Parameter
Value (Clock
Symbol Cycles)
CAS latency
Minimum time between two active commands to different banks
Minimum time between two active commands to same bank
Minimum time between auto refresh and active command
Minimum time after last data write and precharge to same bank
Minimum time between active and precharge command
Minimum time between precharge and active command
Minimum time between active and read command
Minimum time between active and write command
t_CAS
2.5
t_RRD
3
t_RC
8
t_RFC
8
t_WR
1
t_RAS
8
t_RP
4
t_{RCD_RD} 4
t_{RCD_WR} 2
Throughout all timing diagrams a DDR burst size of eight data elements is used.
In the timing diagrams, symbols are used to indicate the DDR commands that are
issued by the DDR controller. An overview of these commands and their symbol
convention are shown in Table 7.
Table 7: DDR Commands
DDR Commands
Symbol
Any DDR command
Any
Activate command
Act
Precharge command
Pre
Read command
Read
Write command
Write
Auto refresh command
A. rf.
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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