PNX17XX Datasheet, PDF (116/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 3: System On Chip Resources
Other than the PCI module, only the TM5250 CPU can emit requests to the PCI bus,
i.e. none of the other PNX17xx Series modules can do so.
Only the TM5250 CPU and external PCI master can request MMIO reads or writes.
The XIO aperture can only be accessed by the TM5250 CPU.
3. System Principles
The system resources module is like any other module composing the PNX17xx
Series system. Like the other modules it has a Module ID MMIO register as well as
powerdown MMIO register.
3.1 Module ID
The module ID MMIO register is used to differentiate between the different modules
of the system and different revisions of the same module. For all the modules the
MMIO content is composed of:
• An unique 16-bit Module ID. This ID is only changed if the functionality of the
Module changes significantly. Module IDs 0 and 1 are reserved.
• An 8-bit revision ID composed of a 4-bit MAJOR_REV ID and a 4-bit
MINOR_REV ID. MAJOR_REV ID is changed upon changing functionality of the
module, while the MINOR_REV ID is changed in case of bug fixing or non
functional fixes like yield improvements.
• An 8-bit value to code the range of recognized MMIO addresses by the module.
This aperture size allows the module to claim one offset region of the MMIO
Aperture. The offset region or local aperture is defined by the following formula,
(N + 1) * 4 Kilobytes, where N is the 8-bit code stored in the module ID register.
This is a read only register. See Section 3.3 for details on the system module ID.
3.2 Powerdown bit
Major powerdown saving is achieved by turning off the clock that feeds the module.
The safe procedure to turn off the clock of a module is to write a ‘1’ to the powerdown
bit located in each module of the system before turning off its clock (whenever it is
possible). Similarly when powering the module back up, the clock should be turned
on before the powerdown bit is flipped back to ‘0’. When the powerdown bit is
activated the module will no longer respond to MMIO read or writes other than
transactions targeting the powerdown bit.
Most of the PNX17xx Series modules need two different clocks to operate. The
streaming clock, e.g. the video pixel clock for QVCP, and the MMIO or DCS clock.
Only the streaming clock should be turned off. Therefore, locally some modules may
do extra clock gating on the DCS clock when the powerdown bit is turned on.
For the system module there is no streaming clock to turn off. Details on the MMIO
register layout is available in the next Section 3.3.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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