PNX17XX Datasheet, PDF (258/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 7: PCI-XIO Module
Table 9: Registers Description
Bit Symbol
Acces
s
Value
Description
24 misc_ctrl
R/W 0
68360: 1 synchronous DSACK; 0 asynchronous DSACK.
NOR: Not used
NAND: Not used
IDE: Not used
23 en_16bit_xio
R/W 0
0 = 8 bit XIO device
1 = 16 bit XIO device
22 sel3_use_ack
R/W 0
0 = Fixed wait state
1 = Wait for ACK
Not used for IDE.
21:18 sel3_we_hi
R/W 0
68360: DS time high.
NOR: WN time high
NAND: REN profile, [19:18] low time; [21:20] high time
IDE: DIOR and DIOW high time
17:14 sel3_we_lo
R/W 0
68360: Not used.
NOR: WN time low
NAND: WEN profile, [15:14] low time; [17:16] high time
IDE: DIOR and DIOW low time
13:9 sel3_wait
R/W 0
68360: DS time low if using fixed timing.
NOR: OEN time low if not using ACK.
NAND: Delay between address and data phase if not using ACK,
delay until monitoring ACK.
IDE: Not used.
8:5 sel3_offset
R/W 0
Starting address offset from start address of XIO aperture, in 8M
increments. This field must be naturally aligned with the size of the
profile.
4:3 sel3_type
R/W 0
Device type selected:
00 = 68360 type device
01 = NOR Flash
10 = NAND Flash
11 = IDE
2:1 sel3_siz
R/W 0
Amount of address space allocated to Sel3 [25,2:1]:
000 = 8M
001 = 16M
010 = 32M
011 = 64M
100 = 128M
0
en_sel3
R/W 0
1 = Enable sel3 profile
Offset 0x04 0838
XIO Sel4 Profile
This register sets up the profile of the XIO select 4line. All times are in reference to PCI clocks.
31:28 Reserved
R
0
27 sel0_offset_ext
R/W 0
Extension field to sel4_offset.
26 Reserved
25 sel0_siz_ext
R/W 0
Extension field to sel4_siz.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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