PNX17XX Datasheet, PDF (505/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 14: FGPI: Fast General Purpose Interface
4. Register Descriptions
Table 2: Register Summary
Offset
Name
Clock
Domain Description
0x07,0000
FGPI_CTL
fgpi
Controls operational mode and enables/disables DMA transfers
0x07,0004
FGPI_BASE1
mmio Starting address for first buffer
0x07,0008
FGPI_BASE2
mmio Starting address for second buffer
0x07,000C
FGPI_SIZE
fgpi
Number of records/messages per buffer
0x07,0010
FGPI_REC_SIZE
fgpi
Size of record/message in samples
0x07,0014
FGPI_STRIDE
fgpi
Address stride between records/messages
0x07,0018
FGPI_NREC1
mmio Number of records/messages transferred into buffer 1
0x07,001C
FGPI_NREC2
mmio Number of records/messages transferred into buffer 2
0x07,0020
FGPI_THRESH1
fgpi
Interrupt Threshold for Buffer 1
0x07,0024
FGPI_THRESH2
fgpi
Interrupt Threshold for Buffer 2
0x07,0028 - reserved
n/a
0x07,0FDC
0x07,0FE0
FGPI_IR_STATUS mmio Module Interrupt Status
0x07,0FE4
FGPI_IR_ENA
mmio Module Interrupt Enables
0x07,0FE8
FGPI_IR_CLR
mmio Module Interrupt Clear (Interrupt Acknowledge)
0x07,0FEC FGPI_IR_SET
mmio Module Interrupt Set (Debug)
0x07,0FF0
FGPI_SOFT_RST mmio Module Software Reset
0x07,0FF4
FGPI_IF_DIS
mmio Module Interface Disable
0x07,0FF8
FGPI_MOD_ID_EXT mmio Module ID Extension
0x07,0FFC FGPI_MOD_ID
mmio Module ID
4.1 Mode Registers
Table 3: Fast general purpose INput (FGPI)
Bit Symbol
Acces
s
Value
FPGI Registers
Offset 0x07,0000
FGPI_CTL
31:15 Reserved
R
0
14 POLARITY_CLK
R/W 0
13 CAPTURE_ENABLE_2 R/W 0
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Externally selects active clock edge for clk_fgpi via fgpi_clk_pol
0 = rising edge
1 = falling edge
Note: This bit not used in the PNX17xx Series. All FGPI clock
control is in the clock module.
Enable input capture into buffer 2. This bit, along with bit 12 below,
start and stop FGPI DMA activity.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
14-18