PNX17XX Datasheet, PDF (309/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 8: General Purpose Input Output Pins
Table 17: GPIO Interrupt Registers for the FIFO Queues (One for each FIFO Queue)
Bit Symbol
Acces
s
Value
Description
3
INT_OE_SET
W
0
Active high internal overrun error interrupt set for queue <0-3>.
2
FIFO_OE_SET
W
0
Active high FIFO overrun error interrupt set for queue <0-3>.
1
BUF2_RDY_SET
W
0
Active high Buffer 2 ready interrupt set for queue <0-3>.
0
BUF1_RDY_SET
W
0
Active high Buffer 1 ready interrupt set for queue <0-3>.
4.12 GPIO Module Status Register for all 12 Timestamp Units
Table 18: GPIO Module Status Register for all 12 Timestamp Units
Bit Symbol
Acces
s
Value
Description
Offset 0x10,4FE0
INT_STATUS4
31:24 Unused
23 INT_OE_11
-
R
0
Internal overrun error in TSU^a 11. Data in TSU overwritten before
read by CPU (i.e before DATA_VALID interrupt was cleared).
22 INT_OE_10
R
0
Internal overrun error in TSU 10. Data in TSU overwritten before
read by CPU (i.e before DATA_VALID interrupt was cleared).
21 INT_OE_9
R
0
Internal overrun error in TSU 9. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
20 INT_OE_8
R
0
Internal overrun error in TSU 8. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
19 INT_OE_7
R
0
Internal overrun error in TSU 7. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
18 INT_OE_6
R
0
Internal overrun error in TSU 6. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
17 INT_OE_5
R
0
Internal overrun error in TSU 5. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
16 INT_OE_4
R
0
Internal overrun error in TSU 4. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
15 INT_OE_3
R
0
Internal overrun error in TSU 3. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
14 INT_OE_2
R
0
Internal overrun error in TSU 2. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
13 INT_OE_1
R
0
Internal overrun error in TSU 1. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
12 INT_OE_0
R
0
Internal overrun error in TSU 0. Data in TSU overwritten before read
by CPU (i.e before DATA_VALID interrupt was cleared).
11 DATA_VALID_11
R
0
Data in TSU 11 is ready to be read.
10 DATA_VALID_10
R
0
Data in TSU 10 is ready to be read.
9
DATA_VALID_9
R
0
Data in TSU 9 is ready to be read.
8
DATA_VALID_8
R
0
Data in TSU 8 is ready to be read.
7
DATA_VALID_7
R
0
Data in TSU 7 is ready to be read.
6
DATA_VALID_6
R
0
Data in TSU 6 is ready to be read.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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