PNX17XX Datasheet, PDF (333/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 9: DDR Controller
2.5.5 Sequence of Actions
To enter halt mode, the DDR SDRAM Controller performs the following sequence of
actions:
1. Precharge all banks (of all ranks)
2. Apply a NOP command
3. Enter self refresh mode, with CKE low, deactivate internal DLL
To leave halt mode, the DDR controller performs the following action:
• 256 DDR SDRAM Controller memory cycles with CKE high, NOP commands, to
activate DLL.
3. Application Notes
3.1 Memory Configurations
The DDR SDRAM Controller supports a wide range of DDR SDRAM memory
configurations. Some examples of memory configurations that are supported for an
external data bus of 32 bits are shown in Figure 8. On the left side a single physical
bank of DDR devices is connected to the DDR controller. Throughout this document
the term rank will be used for a physical bank in order to prevent any confusion with
the logical banks inside the DDR devices. On the right hand side of Figure 8 two
ranks of DDR devices are connected to the DDR controller. In single rank
configurations, there is no need to drive the chip select inputs on the DDR devices
from the DDR controller. In a multi-rank configuration, each rank will receive its own
chip select signal from the DDR controller. The DDR controller offers a 1 to 1 match
with the pin names of the DDR memory devices.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
9-16