PNX17XX Datasheet, PDF (170/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 5: The Clock Module
Clock detection is done based on a 5-bit counter running at the crystal clock
frequency. The implementation detects clocks between 1 MHz and 200 MHz. It will
take up to 2 µs from when the clock is removed until the interrupt condition is
generated. A block diagram of the clock detection circuit is shown in Figure 6.
32
counter
xtal_clk
(external clock)
Toggle
Flop
en
Figure 6: Clock Detection Circuit
en
xtal_clk xtal_clk
clock_present edge
comp
detect
pls2lvl
PIO
INT
intrpt_clk
An interrupt is generated whenever the signal 'clock present' changes status.
Therefore an interrupt is generated if a clock changes from 'present' to 'non-present’
OR from 'non-present to 'present'. The interrupt registers are implemented using the
standard peripheral interrupt module and can thus be enabled/cleared/set by
software.
In the PNX17xx Series all of the above clocks can also be generated internally. In this
case the clock detection circuit can still be enabled. If the internal source is changed
then the clock detection circuit will detect the period of time that there is not a clock.
At this time the logic updates the interrupt status register and asserts an interrupt if
the interrupt is enabled. The interrupts are by default disabled and should remain that
way as long as the clock is generated internally. If in the course of time the output
clock is changed to an input the interrupt status register needs to be cleared before
the interrupts are enabled.
2.10 VDO Clocks
The two VDO out clocks, VDO_CLK1 and VDO_CLK2, have several operating
modes. A brief explanation of these modes is included in this section. Each clock has
three possible modes, input, separate output, and feedback mode. In input mode an
external clock is driving these clocks (hence driving QVCP/LCD and FGPO). In
separate output mode the clock module drives both the clocks going to the IP (QVCP/
LCD and FGPO) and to its related output clock VDO_CLK1 and VDO_CLK2. In this
case the source of the clock is the same, but the paths are totally separate. The third
mode is feedback mode. In feedback mode the clock module drives the output clock,
VDO_CLK1 and VDO_CLK2. This clock is then feedback through the pad to the clock
module. Then it goes on to the IP (QVCP/LCD and FGPO). Diagrams of these clocks
can be found in Figure 17 on page 5-29 and Figure 18 on page 5-29.
To select between output and input mode a bit is provided in each of the configuration
registers for qvcp and fgpo. Writing to the qvcp_output_enable bit will change the
direction of the qvcp clock. Writing to the fgpo_output_enable bit will change the
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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